1. Field of the Invention
The present invention relates to a method of signal transformation for successive approximation for an analog-to-digital converter, and more specifically, to a method with increased resolution.
2. Description of the Prior Art
Recently, thanks to developments in computers, the world is entering the digital era. Videotapes, audiotapes and other analog data storage media are being gradually replaced by digital storage media, such as optical disks. Digital data can be processed by a computer system directly, so the application is more convenient. Generally speaking, analog signals require an analog-to-digital converter (ADC) to be transformed into digital signals. The most common ADC construction includes flash ADC, pipeline ADC and successive approximation ADC. Although flash ADC and pipeline ADC are faster than successive approximation ADC, their electricity consumption is also larger, and are not suitable for many systems with limited power supply.
Please refer to FIG. 1. FIG. 1 is a functional block diagram of a prior art successive approximation ADC 10. The successive approximation ADC 10 comprises a comparator 12, a control logic circuit 13, a successive approximation register (SAR) 14, and a digital-to-analog converter (DAC) 16. The successive approximation register 14 comprises a digital bit stream 18 having a plurality of bits, such as a most significant bit (MSB) 20 and a least significant bit (LSB) 22. The successive approximation register 14 referencing the digital value 18 will output a digital signal 24 to the DAC 16, and then the DAC 16 will transform the digital signal 24 into an analog reference signal 26. The comparator 12 will compare the analog reference signal 26 and an analog input signal 28 to form a comparison result 30. For instance, if the analog reference signal 26 is larger than the analog input signal 28, the comparison result 30 will be binary value xe2x80x9c0xe2x80x9d. On the contrary, if the analog reference signal 26 is smaller than the analog input signal 28, the comparison result 30 will be binary value xe2x80x9c1xe2x80x9d. The control logic circuit 13 based on the comparison result 30 adjusts the digital value 18 stored in the successive approximation register 14 accordingly. As the digital value 18 changes, the digital signal 24 will also change and further influence the magnitude of the output analog reference signal 26 from the DAC 16. This process will continue until the analog reference signal 26 approximates the analog input signal 28 and the least significant bit 22 of digital value 18 is set.
Please refer to FIG. 2 and FIG. 3. FIG. 2 is a block diagram of the DAC 16 shown in FIG. 1 . FIG. 3 is a voltage level diagram of the analog reference signal 26 shown in FIG. 1 The DAC 16 comprises a plurality of switches 34a-d, a plurality of first resistors 36 and a plurality of second resistors 38. The resistance value (2R) of each first resistor 36 is twice the resistance value (R) of each second resistor 38, and the method of electronic connection for the first resistor 36 and the second resistor 38 is a ladder-like architecture used as a voltage divider. Each switch 34 is used to select the voltage input for each first resistor 36, such as a ground (GND) or an operational voltage (Vdd). In addition, every switch 34 maps to a corresponding bit of the digital value 18, and if a bit has a binary value xe2x80x9c1xe2x80x9d in it, the corresponding switch 34 selects operational voltage Vdd. However, if a bit has a binary value xe2x80x9c0xe2x80x9d in it, the corresponding switch 34 selects ground GND. Please note, for easier illustration, FIG. 3 only shows four switches 34a-d, and it is assumed that the bit length of digital value 18 is 4. Among them, switch 34a maps to most significant bit 20, while switch 34d maps to the least significant bit 22. A voltage level of output terminal A from the DAC 16 changes according to the voltage (Vdd or GND) at every switch 34. If the digital value 18 is xe2x80x9c1000xe2x80x9d, switch 34a will connect to Vdd, while switches 34b, 34c, and 34d will all connect to GND. From the voltage divider circuit formed by resistors 36 and 38, we know the voltage level of output terminal A is xc2xd*Vdd. Similarly, if the digital value 18 is xe2x80x9c0100xe2x80x9d, the voltage level of the output terminal A is xc2xc*Vdd. If the digital value 18 is xe2x80x9c0001xe2x80x9d, the voltage level of output terminal A is xe2x85x9*Vdd. If digital value 18 is xe2x80x9c0000xe2x80x9d, the voltage level of output terminal A is {fraction (1/16)}*Vdd. So if D3, D2, D1 and D0 represent digital values 18 from the most significant bit to the least significant bit respectively, by the superposition principle, we can conclude the following relationship between the voltage level Va of output terminal A and the digital value 18:
Va=(xc2xd*D3+xc2xc*D2+xe2x85x9*D1+{fraction (1/16)}*D0)*(Vddxe2x88x92GND)
By changing the bit value of digital value 18, one can further adjust voltage level Va (the reference signal 26 shown in FIG. 1) at output terminal A of the DAC 16. When the successive approximation ADC 10 starts operation, the successive approximation register 14 will set the most significant bit D3 of the digital value 18 to be xe2x80x9c1xe2x80x9d, and the other bits D2xcx9cD0 to be xe2x80x9c0xe2x80x9d.That is, the initial value of the digital value 18 is xe2x80x9c1000xe2x80x9d. So during a first pulse 40a, the voltage level of the analog reference signal 26 is xc2xd*Vdd, as shown in FIG. 3. The voltage level of the analog input signal 28 is greater than the analog reference signal 26, so comparator 12 will transfer the result of comparison 30 into the successive approximation register 14. Because the voltage level of analog reference signal 26 is smaller than analog input signal 28, the successive approximation register 14 keeps the xe2x80x9c1xe2x80x9d in the most significant bit D3, and sets the next bit D2 to xe2x80x9c1xe2x80x9d. Now the digital value 18 is xe2x80x9c1100xe2x80x9d. So during a second pulse 40b, the voltage level of the analog reference signal 26 is (xc2xd+xc2xc)*Vdd. But, the voltage level of the analog input signal 28 is smaller than the analog reference signal 26, so the comparator 12 will transfer the results of comparison 30 into the successive approximation register 14. The successive approximation register 14 will reset bit D2 to xe2x80x9c0xe2x80x9d, and set the next bit D1 to xe2x80x9c1xe2x80x9d, now the digital value 18 is xe2x80x9c1010xe2x80x9d. During a third pulse 40c, the voltage level of the analog reference signal 26 is (xc2xd+xe2x85x9)*Vdd, and the voltage level of the analog input signal 28 is greater than the analog reference signal 26, so the comparator 12 will transfer the result of comparison 30 into the successive approximation register 14. As described, the successive approximation register 14 keeps the xe2x80x9c1xe2x80x9d in bit D1, and sets the next bit to xe2x80x9c1xe2x80x9d, and the digital value 18 becomes xe2x80x9c1011xe2x80x9d. Finally, during the fourth pulse 40c, the voltage level of the analog reference signal 26 is (xc2xd+xe2x85x9+{fraction (1/16)})*Vdd, and the voltage level of the analog input signal 28 is greater than the analog reference signal 26, so the comparator 12 transfers the result of comparison 30 into the successive approximation register 14. As described, the successive approximation register 14 keeps the xe2x80x9c1xe2x80x9d in bit D0. Since bit D0 is the least significant bit, the successive approximation ADC 10 is finished one signal transformation process, that is, the analog input signal 28 is finally transformed into digital output signal 32 shown in FIG. 1 (xe2x80x9c1011xe2x80x9d).
As described above, the successive approximation ADC 10 use the prior art binary search algorithm to detect voltage levels of the analog input signal 28 to produce the digital output signal 32. For a successive approximation ADC 10 to transform an analog input signal 28 into a 4-bit digital output signal 32, the smallest output quantity value that the DAC 16 can produce is {fraction (1/16)}*Vdd, this being the resolution of the successive approximation ADC 10. If the successive approximation register 14 uses more bits (e.g. 10 bits) for the digital value 18, this relatively improves the resolution of the successive approximation ADC 10 (e.g. 1/1024*Vdd) allowing measurement of the analog input signal 28 with better accuracy producing a more accurate output signal 32. In general, the successive approximation ADC 10 is an integrated circuit (IC), produced by semiconductor processes. Normally, it will incorporate one conductor layer or impurity doped layer to form a resistor component, such resistor component being influenced by the process and having an error between the actual resistance and ideal value. That is, there cannot be a completely accurate predefined ratio (2:1) of the resistances of resistors 36 and 38. Because the DAC 16 uses voltage divider architecture formed by resistors 36 and 38 to produce matching voltage levels by the binary search method, the error of each resistance further influences the least quantified value of the DAC 16, i.e. the resolution. Thus, when the DAC 16 uses the binary search to compare the voltage level of the input signal 28 to the analog reference signal 26, the inaccurate analog reference signal 26 causes errors from the ideal value in the actual digital output signal 32.
It is the primary objective of the claimed invention to provide a signal transformation method for a successive approximation ADC to improve resolution to solve the problems described above.
Briefly summarized, the claimed invention provides a method of signal transformation in an analog-to-digital converter (ADC). The ADC is used to transform an analog input signal to a digital output signal. The ADC comprises a successive approximation register (SAR) to store a digital value with a predetermined bit length, and one digital-to-analog converter (DAC). The ADC further comprises a first voltage divider unit with an input terminal electrically connected to a first predetermined voltage, a second voltage divider unit with an input terminal electrically connected to the first predetermined voltage, and a third voltage divider unit. The first voltage divider unit comprises a first resistor that is used to approach a first resistance, and a first switch that Is electrically connected to the first resistor for controlling whether the output terminal of the first voltage divider unit is electrically connected to the input terminal. The second voltage divider unit comprises a second resistor that is used to approach the first resistance, and a second switch that is electrically connected to the second resistor for controlling whether the output terminal of the second voltage divider unit is electrically connected to the input terminal. The third voltage divider unit comprises a plurality of third resistors, each having a resistance approaching the first resistance value; a plurality of fourth resistors connected in series between the output end of the first voltage divider unit and the output end of the second voltage divider unit, each fourth resistor having a resistance approaching a second resistance value and both ends of each fourth resistor connected to two adjacent third resistors; and a plurality of control switches. Each control switch comprisesa third switch connected between a third resistor and the first predetermined voltage and a fourth switch connected between a third resistor and a second predetermined voltage. The signal converting method comprises controlling the first switch and the second switch to electrically connect the first voltage divider unit to the first predetermined voltage and to disconnect the second voltage divider unit from the first predetermined voltage, controlling the plurality of control switches for the output end of the second divider unit generating a first voltage approaching the analog input signal, and controlling the successive approximation register generating a first digital bit stream according to the first voltage. The method further comprises controlling the first switch and the second switch to disconnect the first voltage divider unit from the first predetermined voltage and to electrically connect the second voltage divider unit to the first predetermined voltage, controlling the plurality of control switches for the output end of the first divider unit generating a second voltage approaching the analog input signal, and controlling the successive approximation register generating a second digital bit stream according to the second voltage. The method finally comprises computing an average of the first digital bit stream and the second digital bit stream to generate the digital output signal.
These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.